This invention generally relates to designing integrated circuits (ICs) and more specifically to simplifying the schematic diagram of an IC design.
One of the processes in the design cycle of an IC involves defining the IC design at the register transfer level (RTL), where a designer determines the flow of signals between hardware registers and the logical operations performed on the signals. In an RTL design, the designer uses a hardware design language (HDL) to declare the registers and describe the combination logic by using constructs that are similar to those in standard programming languages such as if-then-else and arithmetic operations. Examples of HDL include Verilog and VHDL.
Electronic design automation (EDA) software is commonly used in designing ICs. By using EDA software during a process called synthesis in the design cycle of an IC, the HDL file can be converted to an equivalent netlist containing the generic hardware primitives to implement the logic specified in the HDL file.
Generally speaking, a netlist contains information concerning the number and types of elements in an IC design and the manner in which they are interconnected. In a netlist, the interconnected circuit elements, typically referred to as nodes, may be as simple as a resistor, or as complex as a microprocessor. The wires that connect the circuit elements are commonly referred to as nets. A typical netlist might include a list of circuit elements connected on a common net.
As market demand drives electronics companies to pack more performance and functionality into chips of ever-smaller geometries, the complexity of netlists has also increased tremendously, resulting in schematic diagrams that are invariably visually crowded and extremely difficult to manipulate when displayed for a user. Subsequently, synthesis problems require a greater amount of time to analyze and debug.
Netlist viewers typically provide a graphical user interface (GUI) to represent the schematic diagram of a netlist. With a netlist viewer, designers can check their designs visually to ensure that the connections and logic meet all requirements before simulation and other verification processes. Viewing a netlist represented in the form of a schematic diagram is a powerful way to analyze, debug, and optimize an IC design. For example, designers can move backwards and forwards in a schematic diagram and also move through levels of grouping hierarchy to find certain nodes or locate a specific net by visually inspecting the diagram.
The growing complexity of netlists necessitates the need for ways to render the schematic diagram in a less cluttered manner. A schematic diagram that hides the unnecessary implementation details without changing, the underlying logic eases the analysis, debugging, and optimization processes. Conventionally, a schematic diagram can be simplified in a number of ways, including:    a) Changing the original source (e.g., the HDL specification) and generating a new netlist to be displayed on the netlist viewer. This option is tedious and time-consuming because the HDL design requires recompilation every time the code is changed.    b) Editing the schematic diagram on the netlist viewer through the GUI.
Many EDA software tools provide netlist simplification features, which include at least one of the following:    a) Grouping and ungrouping of nodes. However, the nodes that can be grouped or ungrouped must already be defined as hierarchical instances in the HDL design. Thus, users cannot remove nodes from an existing group or add new and unrelated nodes into an existing group.    b) Filtering of nodes. With the filtering feature, users can filter out nodes and nets in a netlist to display only the logic and connections that are of interest. However, the filtering criteria are fixed by the program and users cannot bypass the fixed netlist modification program to modify the netlist directly based on their own criteria.    c) Grouping nodes into “clouds”. A cloud comprises a group of combinational logic nodes. With the cloud-grouping feature, users can choose to hide the combinational logic in the schematic diagram by grouping them into clouds. The cloud-grouping feature is based on a fixed set of criteria defined in the software. Users can turn the cloud-grouping feature on or off; but do not have the flexibility to change the criteria for grouping the clouds. Furthermore, the cloud-grouping feature can be used on only combinational logic elements.    d) Partitioning nodes into multiple pages. The partitioning feature merely reduces the amount of detail per page, but does not hide the unnecessary details. Users still have to move from page to page while traversing through an unwieldy schematic diagram.
Examples of EDA software and netlist viewers include the following:    a) Active HDL from Aldec, Inc. of Henderson, Nev.;    b) Composer from Cadence Design Systems, Inc. of San Jose, Calif.;    c) Design Compiler Graphical from Synopsys, Inc. of Mountain View, Calif.;    d) DxDesigner from Mentor Graphics, Inc. of Wilsonville, Oreg.;    e) ISE from Xilinx, Inc. of San Jose, Calif.;    f) Leonardo Spectrum from Mentor Graphics, Inc. of Wilsonville, Oreg.;    g) Matrix from Altera, Inc. of San Jose, Calif.;    h) Quartus II from Altera, Inc. of San Jose, Calif.;    i) Synplify from Synopsys, Inc. of Mountain View, Calif.;    j) Undertow from Veritools, Inc. of Palo Alto, Calif.; and    k) ViewDraw from Aldec, Inc. of Henderson, Nev.
Generally speaking, many of the netlist viewers today provide a fixed set of criteria when it comes to reducing the number of nodes and nets on a schematic diagram and do not provide users the flexibility to simplify the schematic diagram based on their own requirements.